1. Field of the Invention
This invention concerns a process for synchronization to an interference prone reference signal frequency.
2. Description of the Prior Art
According to CCITT recommendation G.811, international digital communications connections should be operated with a long-term relative signal frequency deviation of less than 1.times.10.sup.-11, which corresponds to a drift of approximately one frame in 70 days. In plesiochronic operation, i.e., "free running" operation, this frequency constancy can be achieved only with expensive cesium atomic frequency standards.
In order to be able to maintain the recommended frequency constancy even in the national network, an economically and technologically favorable solution is a synchronous digital system whereby the clock signal generators of the exchange (starting from a central reference or standard clock source) are synchronized to a reference signal frequency f.sub.R, which is transmitted, for example, from one network center of the same or higher order over an existing digital signal connection with this network center. In the event of an interruption in such a connection, the reference signal frequency is supplied on an alternative route from another one of these network centers.
It is known that a digital phase control circuit according to FIG. 1 can be used for such synchronization. The design and function of this control circuit are described here briefly.
The signal frequency f.sub.s of an exchange was divided down by a frequency divider FDS and is optionally synchronized to one of two reference frequencies f.sub.R0 or f.sub.R1, which are supplied from different exchanges of the same or higher order as explained elsewhere.
Depending on the switch position of a reversing switch S.sub.u, one of the two reference frequencies is applied to the first input of a phase discriminator PD as a standardized input frequency f.sub.i by way of the frequency dividers FD0 and FD1. The second input receives the reference frequency f.sub.0, which is derived via a loop counter LC from the output frequency f.sub.n of a voltage controlled oscillator VCO that is acted on by the frequency divider FDS to generate f.sub.s.
In accordance with the control algorithm of the processing unit (microprocessor) MP a control value is calculated from the phase difference between the two frequencies f.sub.i and f.sub.o and is sent as the control voltage to the voltage controlled oscillator (VCO) by way of a digital-analog converter DAC.
The jitter and drift disturbances superimposed on the reference frequencies are treated in accordance with CCITT recommendation Q 502, i.e., high-frequency jitter disturbances are damped according to a low pass characteristic, whereas drift disturbances (daily drift) are relayed.
When it is necessary to switch to a different reference frequency (e.g., from f.sub.R0 to f.sub.R1) or in the event of sudden phase shifts in the input frequency f.sub.i (without switching), the loop counter LC is reset by a phase correction PC, so the instantaneous phase difference at the input of the phase discriminator is set at zero. The reset time is selected so it coincides with a change in edge (trailing or leading) of the input frequency f.sub.i. This should prevent unnecessary frequency changes in the oscillator due to correction of the phase shift.
However, this measure also results in simultaneous loss of the original phase relationship between the input frequency f.sub.i and the reference frequency f.sub.o which was established on the basis of the preceding control process. After resetting loop counter LC, this steady-state phase relationship can be gradually restored (according to the time constants of the phase control circuit) but interference processes (e.g., jitter, drift, aging) during the transition phase and up until restoration of the steady-state relationship can cause a permanent phase deviation. Even phase deviations (jitter) that would be reset back to their steady-state level after the transition phase become permanent phase deviations when it is necessary to reset the loop counter within this period of time.
In contrast with the case described previously, there is no relationship between the phase position of the signal frequency or the reference frequency f.sub.o and the phase of the new reference frequency before the resetting which is necessitated by the switching. In the worst case, this results in an accumulation of the phase deviation as shown in to FIG. 2.
It is assumed in FIG. 2 that the two reference frequencies f.sub.R0 and f.sub.R1 involved in the switching U have periodic phase deviations .DELTA.R.sub.R0 and .DELTA.W.sub.R1 in comparison with the normal frequency which are exactly opposite each other due to drift. If switching is performed precisely at the times t.sub.0, t.sub.1, t.sub.2, and t.sub.3 of the maximum phase deviation, the oscillator will oscillate constantly at a somewhat increased frequency f.sub.n, so the phase deviation .DELTA.W.sub.s of the signal frequency f.sub.s is increased steadily in comparison with the normal frequency.
Statistically, the accumulation of phase deviation .DELTA.W.sub.s due to the resetting processes can be described by the random walk model. In this model each resetting process is interpreted as an interference event with an average frequency h and a permanent average phase deviation .+-..DELTA.W.sub.s. The standard deviation .epsilon. of the phase deviation .DELTA.W.sub.s is then obtained according to the following equation, where the parameter t characterizes the time. ##EQU1##
An object of the present invention is to reduce the random walk of the phase and the network.